Methods of deriving switch networks

ABSTRACT

A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch networks to be implemented as standard cells implementations of combinational logic cells. The minimum number of switches can also be used as a criterion for technology mapping devoted to automatic cell generation. The method is based on the use of a covering table to derive a sum of products where individual cubes have a minimum literal count.

This application is a divisional of application Ser. No. 11/711,828filed Feb. 28, 2007, which claims the benefit of priority under 35U.S.C. §119 from U.S. Patent Application No. 60/777,561, filed on Mar.1, 2006 in the United States Patent and Trademark Office, the contentsof each of which are herein incorporated by reference in their entiretyfor all purposes.

The present invention relates to methods of obtaining switch networkswith optimized parameters and in particular to a method of ensuring thatthe number of serial transistor of each plane or sets of pathsconnecting the output to a given value of a function is minimized. Theobject of the invention is to provide cells with the same functionalitybut with a reduced logical effort. A reduced logical effort can betranslated into a reduction of area, power and/or delay when designingan integrated circuit.

Technology of this type may be seen in U.S. Pat. No. 7,003,738.

In a first aspect, the invention relates to a method of deriving aswitch network adapted to carry out a multiple-valued function, such asa function defined by a truth table, and comprising a network relatingto each of the multiple values of the function, the method comprising:

-   -   deriving one potential network for each of the multiple values        of the function and using each of a plurality of different        methods, and    -   for each of the multiple values of the function, selecting, as        the derived, potential network of the value of the function and        of the switch network, one of the derived networks for the        value,        where the selected networks are derived by different methods.

In the present context, a switch network is a plurality ofinterconnected switches adapted to change characteristics (normallychange a conducting behaviour) as a result of an input signal. Theseswitches may be transistors, nanotubes, valves, relays, neurons, or thelike.

A network of switches is adapted to carry out a function when the inputsof the function are the inputs to the switches and when the behaviour ofthe switches determines the output signal on an output of the network inaccordance with the output of the function on the basis of the sameinputs. A multiple-valued function is a function able to provide anoutput being chosen between a plurality of different possible values. Amultiple-valued function having only two possible output values and twopossible input values is a Boolean function.

Normally, a multiple-valued function may be described by a truth tabledescribing the output of the function as a function of the possibleinputs thereof.

In the present context, a network relating to a value of the functionwill be a network usually interconnecting a supply voltage representingthe value of the function and the output. This network will comprise anumber of switches, the inputs and behaviour of which interconnect theoutput to this voltage, when the output of the function requiresthis—and does not when the function requires that. Normally, only asingle of these networks interconnects the output to a given voltage.

The overall network implementing the function may be divided up intonetworks relating to the different values of the function. Switches maybe part of more than one of these networks.

In the present context, and as it will be described further below, alarge number of methods exist of deriving networks either for a fullfunction or for each of the networks thereof relating to an output valuethereof. Some of these methods actually comprise firstly deriving onenetwork for one output value and then deriving a network relating toanother output value from the first network.

The finally selected networks may be represented individually or as anassembled/interconnected network representing the full function.

In the present context, two methods are different if they result indifferent networks representing the same value of the same function. Inthe present context, networks are primarily different, if they comprisedifferent numbers of switches or have different numbers of parallel orserial switches between the output and the voltage corresponding to thevalue of the function (normally a supply voltage).

Preferably, the selecting step comprises selecting, as the networkrelating to the value of the function the derived, potential networkhaving the lowest number of serial switches, normally between the outputand a voltage supply. Having a low number of serial switches has anumber of advantages both in speed and power consumption of the overallnetwork.

In a particular embodiment, the selecting step comprises the steps of:

-   -   estimating a lowest number of serial switches of one or more of        the networks by        -   deriving from the function (such as from a truth table of            the function) a covering table relating to the actual value            of the function and having a number of cubes each covering            one or more minterms,        -   determining the lowest number of serial switches of the            network as the number of literals in a cube having the            largest number of literals and covering a minterm not            covered by a cube having a lower number of literals, and    -   selecting the network as a derived, potential network of the        value of the function, the network fulfilling a predetermined        criterion relating to the number of serial switches therein, the        determined lowest number of serial switches, and/or the total        number of switches in the potential network relating to the        value of the function.

In the present context, a covering table is a table that relates cubesto the minterms covered by the cubes. In a covering table, the entriesof the actual value of the function have been replaced by “1”'s and theremaining values with “0”'s (or any two values different from eachother). In this situation, a cube is a product of literals, and literalsare the variables of the function—or their complements.

A minterm is a cube containing one literal associated to each variableof the function. A minterm may be called an implicant minterm if, whenthe input variables thereof are presented to the function, this resultsin the function outputting the output value in question for the coveringtable.

A cube is an implicant cube if the minterms covered thereby are allimplicant minterms. Preferably the cubes used in the present methods arethe implicant cubes of the covering table.

A covering table comprises a number of prime implicant cubes which arethose implicant cubes which are defined by the fewest literals. Thus, aprime implicant cube is an implicant cube from which, if a literal isremoved, it is no longer an implicant cube. Preferably, a covering tablewill contain all possible prime implicant cubes and only those. Theprime implicant cubes may be represented explicitly or implicitly in thecovering table.

In the present context, a covering table may be represented in anysuitable manner, such as a table, a list, a linked list, linked recordsor the like, normally stored in an electronic memory, such as a ROM,RAM; PROM, EPROM, EEPROM, or the like.

It should be noted that it is not required to actually remove e.g. cubeshaving a larger number of literals than the cube having the largestnumber of literals and covering a minterm not covered by a cube having alower number of literals. The present lowest number may be determinedfrom the cubes as present in the covering table.

When generating a network, it may be desired to take into account asubset of cubes from the covering table such that it does not containany cube covering only minterms covered by other cubes in the subset.This will be described further below.

In one situation, the selecting step comprises the step of selecting, asthe network relating to the value, a potential, derived network having anumber of serially connected switches equal to the determined lowestnumber of serial switches. In this manner, it is ensured that thenetwork selected has e.g. a high speed.

In another situation, the selecting step comprises the step ofselecting, as the network relating to the value, a potential, derivednetwork having the lowest total number of switches. A low total numberof switches reduces the power consumption of the network, which is alsoa desired parameter.

In addition to using the above method for determining the lowest numberof serial switches, it may also be used for other purposes.

In an interesting embodiment, the deriving step comprises deriving apotential network by

-   -   deriving from the function (such as from a truth table of the        function) a covering table for the pertaining value of the        function and having a number of cubes each covering one or more        minterms,    -   estimating the lowest number of serial switches in the network        as the number of literals in a cube having the largest number of        literals and covering a minterm not covered by a cube having a        lower number of literals (i.e. the number of literals in that or        those of the cubes, which each covers a minterm not covered by a        cube having a lower number of literals, and which has the most        literals), and    -   deriving the network on the basis of cubes of the covering table        having a number of literals smaller than or equal to the        estimated lowest number of serial switches of the network, the        network having a number of parallel paths, each parallel path        being defined by a cube and having a number of serially        interconnected switches each having an input corresponding to a        literal of the cube.

Normally, the parallel paths will, at their outer ends, be connected toeach other and to the output at one end and a supply voltage at theother end.

Thus, by using this method, it is ensured that a network having thelowest possible number of serial switches from the output to the voltage(normally a supply voltage) is generated. It should be noted thatswitches may be shared between the individual paths, and that there area number of manners of improving the network derived by this method.

In one situation, it is desired to provide the parallel paths of allcubes having a number of literals equal to or lower than the determinedlowest number of serial switches in order to ensure that the fullfunction of the function is maintained. However, it may be desired toprovide this with a lower number of switches. This may be obtained, whenthe deriving step comprises deriving the network from only a subset ofthe cubes of the covering table having a number of literals smaller thanor equal to the estimated lowest number of serial switches of thenetwork, where each cube in the subset covers at least one minterm notcovered by other cubes of the subset. In this manner, some of the paths(defined by the cubes no longer used) are removed, reducing the totalnumber of switches of the network without affecting the overallfunctionality of the network.

In addition, it may be desired to have the method further comprise thestep of improving a selected network by:

-   -   identifying two parallel paths each comprising a switch having        the same input and    -   changing one of the identified paths to share the switch of the        other identified path (or a new switch now common to both paths)        with that input.

This method may be performed repeatedly for many or all switches orpaths in that network in order to further improve the network.

Yet another manner of improving the network is one further comprisingthe steps of:

-   -   determining an ordering of the inputs of the switches, from        lowest to highest,    -   defining a direction in a path of the network, and    -   interchanging positions of two switches of the path if a lower        order switch is positioned, along the direction, before a higher        order switch.

In this context, the ordering may be one of e.g. power consumption orthe switching velocity/timing of the switches. In addition, thedirection of the path in the network normally is from the voltage(normally a supply voltage) to the output of the network.

Moving switches with higher probability of switching (such as switchescontrolled by the clock signal) to a position closer to the output ofthe network may reduce the overall power consumption of such network inthat fewer nodes will then have to be charged for each switching of thissignal. In addition, moving slower switches to positions closer to theoutput will reduce the negative impact of such devices on the networkspeed.

In a second aspect, the invention relates to a method of deriving aswitch network adapted to carry out a predetermined multiple-valuedfunction and comprising a network for each of the multiple values of thefunction, the method comprising:

-   -   for at least one of the networks relating to a value of the        function:        -   deriving from the function (such as from a truth table of            the function) a covering table for the pertaining value of            the function and having a number of cubes each covering one            or more minterms,        -   estimating the lowest number of serial switches in the            network as the number of literals in a cube having the            largest number of literals and covering a minterm not            covered by a cube having a lower number of literals, and        -   deriving the network on the basis of the cubes of the            covering table having a number of literals smaller than or            equal to the estimated lowest number of serial switches of            the network relating to the value of the function, the            network having a number of parallel paths, each parallel            path being defined by one cube and having a number of            serially interconnected switches each having an input            corresponding to a literal of the cube.

As mentioned above, it is not required to remove cubes from the coveringtable in order to be able to generate the network.

It is clear that cubes having a number of literals higher than theestimated lowest number of serial switches are not used. In addition, itis advantageous, however, that the deriving step comprises deriving thenetwork from a subset of the cubes having a number of literals smallerthan or equal to the estimated lowest number of serial switches of thenetwork relating to the value of the function, where each cube in thesubset covers at least one minterm not covered by other cubes of thesubset.

As mentioned above, preferably the deriving step comprises the steps of:

-   -   identifying two parallel paths each comprising a switch having        the same input and    -   changing one of the identified paths to share the switch of the        other identified path with that input. Again, this may be        performed repeatedly for many or all switches or paths in that        network.

Also, the deriving step could comprise the steps of:

-   -   determining an ordering of the inputs of the switches, from        lowest to highest,    -   defining a direction in a path of the network, and    -   interchanging positions of two switches of the path if a lower        order switch is positioned, along the direction, before a higher        order switch.

A third aspect of the invention relates to a method of determining alowest number of serial switches in a switch network representing avalue of a multiple-valued function, the method comprising:

-   -   deriving from the function (such as from a truth table thereof)        a covering table associated to the value and having a number of        cubes each covering one or more minterms, and    -   determining the lowest number of serial switches as the number        of literals in a cube having the largest number of literals and        covering a minterm not covered by a cube having a lower number        of literals.

In the present context, a network represents a value of a function whenthe function outputs the value as a result of the correct inputs, asdefined by the function. The function may be defined by a truth table.

As mentioned above, the covering table may comprise also non-primeimplicant cubes, and it is not required to remove cubes from thecovering table in order to determine the lowest possible number ofserial transistors.

Different manners exist of determining the cube in question (i.e. a cubehaving the largest number of literals and covering a minterm not coveredby a cube having a lower number of literals). One such manner is onewherein the determining step comprises the steps of:

-   -   determining, for each minterm, a cube covering the minterm and        having the smallest number of literals, and    -   determining the lowest number of serial switches as the number        of literals in a cube having the largest number of literals        among the determined cubes.

Another method is one wherein the determining step comprises the stepsof:

-   -   repeatingly identifying, in the covering table, a cube having a        largest number of literals and determining whether each minterm        which is covered by the identified cube is also covered by        another cube having a lower number of literals, if so, removing        the cube from the covering table,    -   until no cube can be removed, and    -   determining the lowest number of serial switches as the number        of literals in a cube having the largest number of literals in        the covering table.

Instead of removing, it may suffice to mark the cubes and thereafter notuse these again, so that the lowest number of serial switches isdetermined on the basis of non-marked cubes.

A fourth aspect of the invention relates to what may be calledtechnology mapping of circuits or networks. More particularly, thisaspect relates to a method of mapping a function or a network ofswitches, the method comprising:

-   -   for each of a plurality of parts of the function or the network,        determining a logic sub-function implemented thereby and, for        each of the values of the function, determining a lowest number        of serial switches of a network representing the value of the        sub-function, using the method according to the third aspect of        the invention, and    -   selecting a subset of the determined parts, the parts of the        subset implementing the function, and where each part, for each        of the networks relating to a value of the sub-function of the        part, has a lowest number of serial switches lower than a        predetermined value.

Preferably, if the mapping is of a function, the function is describedas a set of interconnected logic primitives, such as and-gates,or-gates, inverters or the like.

In this context, the full function or network is implemented by theparts when all parts of the function or network are present in at leastone part.

The present method may be used on particular parts, such as partsidentified using a predetermined search strategy, or thefunction/network may be divided into a plurality of parts, where allparts at least cover the full function/network once, and where all partsare then analyzed.

Preferably, a window defining the parts is moved stepwise over thefunction or network in a manner so that overlapping areas are definedand analyzed in order to identify the best division of the network andthereby the best potential improvement thereof.

In the present context, a sub-function implemented by a network presentin a part is a logic function implemented by the logics of the network.Any network may be analyzed to result in a truth function or a functionimplemented thereby.

The overall analysis of the network/function results in a selection ofparts (and a dividing of the network) which may be optimized as to thenumber of serial switches in each sub-network (relating to each of thevalues of the function). Another manner of dividing the network/functionwould be one wherein the subset is selected such that a given costfunction for the overall function or network is minimized. This costfunction may be total number of switches of the parts. The total numberof switches has an influence on the overall area taken up, the powerconsumption as well as the speed of the function/network.

A fifth aspect of the invention relates to a method of improving anetwork or function, the method comprising:

-   -   defining a part of the function or the network, determining a        logic sub-function implemented thereby and, for each of the        values of the function, determining a lowest number of serial        switches of a network representing the value of the        sub-function, using the method according to the third aspect of        the invention, and    -   replacing the part of the function or network by a network of        switches, representing the sub-function and derived as described        in relation to the second aspect of the invention.

Consequently, the dividing of the network/function may be as describedin relation to the fourth aspect.

A sixth aspect of the invention relates to a computer program adapted tocontrol a processor to carry out the process of any of the above aspectsof the invention. Thus, a network or function is entered thereinto, andinformation relating to a network having a number of advantages isgenerated.

The above methods have been described in general for multiple-valuedfunctions, including Boolean functions being a subgroup thereof havingonly two possible output values.

A seventh aspect of the invention relates to a method of deriving aswitch network adapted to carry out a Boolean function and comprising apull-up network and a pull-down network, the method comprising:

-   -   deriving one potential pull-up network and one potential        pull-down network using each of a plurality of different        methods,    -   selecting, as the pull-up network of the switch network, one of        the derived pull-up networks, and    -   selecting, as the pull-down network of the switch network, one        of the pull-down networks,        where the selected pull-up network and the selected pull-down        network are derived by different methods.

In the present context, a pull-up network is a network representing the“1” or pull-up value of the function and is a network connecting theoutput to a higher voltage (such as a supply voltage) upon providing ofthe correct inputs to the switches of this network.

Also, the pull-down network is the network connecting the output to alower voltage, such as ground or zero, upon providing of the correctinputs of the switches thereof.

As mentioned in relation to the first aspect of the invention, themethods will normally be different, if networks are generated, for thesame value of the same function, having different numbers of serialswitches or different total numbers of switches.

Also, as mentioned in relation to the first aspect, the final networkmay be represented by a mix of the two networks, where switches mayactually be shared by the two networks.

Preferably, at least one of the selecting steps comprises selecting asthe pull-up/down network a potential pull-up/down network having thelowest number of serial switches (normally between the output and asupply voltage).

In an interesting embodiment, the step of selecting the pull-up networkcomprises the steps of:

-   -   estimating a lowest number of serial switches in the pull-up        network by        -   deriving from the function (such as from the Boolean table)            a covering table of the function, which may comprise also            non-prime implicant cubes, having a number of cubes each            covering one or more minterms, and        -   determining the lowest number of serial switches as the            number of literals in a cube having the largest number of            literals and covering a minterm not covered by a cube having            a lower number of literals, and    -   selecting the pull-up network as a derived, potential pull-up        network fulfilling a predetermined criterion relating to the        number of serial switches therein, the determined lowest number        of serial switches, and/or the total number of switches in the        potential pull-up network.

In that or another embodiment, the step of selecting the pull-downnetwork may also comprise the steps of:

-   -   estimating a lowest number of serial switches in the pull-down        network by        -   deriving (such as from the inverted Boolean table) a            covering table of the inverted function and having a number            of cubes each covering one or more minterms, and        -   determining the lowest number of serial switches as the            number of literals in a cube having the largest number of            literals and covering a minterm not covered by a cube having            a lower number of literals, and    -   selecting the pull-down network as a derived, potential        pull-down network fulfilling a predetermined criterion relating        to the number of serial switches therein, the determined lowest        number of serial switches, and/or the total number of switches        in the potential pull-down network.

In any of the two above embodiments, the selecting step may comprise thestep of selecting, as the pull-up/down network, the potentialpull-up/down network having a number of serially connected switchesequal to the determined lowest number of serial switches.

Also, in any of the above two embodiments, the selecting step maycomprise the step of selecting, as the pull-up/down network, thepotential pull-up/down network having the lowest total number ofswitches.

In an interesting embodiment, the deriving step of deriving a potentialpull-up network comprises:

-   -   deriving from the function (such as from the Boolean table) a        first covering table having a number of cubes each covering one        or more minterms,    -   estimating the lowest number of serial switches in the pull-up        network as the number of literals in a cube of the first        covering table having the largest number of literals and        covering a minterm not covered by a cube having a lower number        of literals, and    -   deriving the pull-up network on the basis of cubes of the first        covering table having a number of literals smaller than or equal        to the estimated lowest number of serial switches of the pull-up        network, the network having a number of parallel paths (where        individual switches may be shared between paths), each parallel        path being defined by one cube and having a number of serially        interconnected switches each having an input corresponding to a        literal of the cube.

In the same or another embodiment, the deriving step of deriving apotential pull-down network comprises:

-   -   deriving (such as from the Boolean table) from the inverted        function a second covering table having a number of cubes each        covering one or more minterms,    -   estimating the lowest number of serial switches in the pull-down        network as the number of literals in a cube of the second        covering table having the largest number of literals and        covering a minterm not covered by a cube having a lower number        of literals, and    -   deriving the pull-down network on the basis of cubes of the        second covering table having a number of literals smaller than        or equal to the estimated lowest number of serial switches of        the pull-down network, the network having a number of parallel        paths (where individual switches again may be shared between        paths), each parallel path being defined by one cube and having        a number of serially interconnected switches each having an        input corresponding to a literal of the cube.

In any of the above two embodiments, the deriving step may comprisederiving the network either from all cubes having a number of literalslower than or equal to the lowest number of serial switches or from asubset of the cubes having a number of literals smaller than or equal tothe estimated lowest number of serial switches, where each cube in thesubset covers at least one minterm not covered by other cubes in thesubset.

Preferably, the method further comprises the steps of improving aselected network by:

-   -   identifying two parallel paths each comprising a switch having        the same input and    -   changing one of the identified paths to share the switch of the        other identified path with that input.

These steps may be performed repeatedly for many or all switches orpaths in that network. Also, the method may further comprise the stepsof improving a selected network by:

-   -   determining an ordering of the inputs of the switches, from        lowest to highest,    -   defining a direction in a path of the network, and    -   interchanging positions of two switches of the path if a lower        order switch is positioned, along the direction, before a higher        order switch.

An eighth aspect of the invention relates to a method of deriving aswitch network adapted to carry out a predetermined Boolean function andcomprising a pull-up network and a pull-down network, the methodcomprising:

-   -   deriving from the function (such as from the Boolean table) a        first covering table (which may comprise also non-prime        implicant cubes) having a number of cubes each covering one or        more minterms,    -   estimating the lowest number of serial switches in the pull-up        network as the number of literals in a cube of the first        covering table having the largest number of literals and        covering a minterm not covered by a cube having a lower number        of literals,    -   deriving the pull-up network on the basis of cubes of the first        covering table having a number of literals smaller than or equal        to the estimated lowest number of serial switches of the pull-up        network, the network having a number of parallel paths (where        individual switches may be shared between paths), each parallel        path being defined by one cube and having a number of serially        interconnected switches each having an input corresponding to a        literal of the cube,    -   deriving from the inverted function (such as from the Boolean        table) a second covering table (which again may comprise also        non-prime implicant cubes) having a number of cubes each        covering one or more minterms,    -   estimating the lowest number of serial switches in the pull-down        network as the number of literals in a cube of the second        covering table having the largest number of literals and        covering a minterm not covered by a cube having a lower number        of literals, and    -   deriving the pull-down network on the basis of cubes of the        second covering table having a number of literals smaller than        or equal to the estimated lowest number of serial switches of        the pull-down network, the network having a number of parallel        paths (where individual switches again may be shared between        paths), each parallel path being defined by one cube and having        a number of serially interconnected switches each having an        input corresponding to a literal of the cube.

In that aspect, the deriving step preferably comprises deriving thenetwork from either all cubes of the covering table or a subset of thecubes of the covering table, where each cube in the subset covers atleast one minterm not covered by other cubes of the subset.

In addition, the deriving step may comprise the steps of:

-   -   identifying two parallel paths each comprising a switch having        the same input and    -   changing one of the identified paths to share the switch of the        other identified path with that input.

As mentioned above, these steps may be performed repeatedly for many orall switches or paths in that network.

Also, the deriving step may comprise the steps of:

-   -   determining an ordering of the inputs of the switches, from        lowest to highest,    -   defining a direction in a path of the network, and    -   interchanging positions of two switches of the path if a lower        order switch is positioned, along the direction, before a higher        order switch.

A ninth aspect of the invention relates to a method of determining alowest number of serial switches in a pull-up network of a switchnetwork adapted to carry out a Boolean function, the method comprising:

-   -   deriving, from the function, a covering table having a number of        cubes each covering one or more minterms,    -   determining the lowest number of serial switches as the number        of literals in a cube having the largest number of literals and        covering a minterm not covered by a cube having a lower number        of literals.

A tenth aspect of the invention relates to a method of determining alowest number of serial switches in a pull-down network of a switchnetwork adapted to carry out a Boolean function, the method comprising:

-   -   deriving, from the inverted function, a covering table having a        number of cubes each covering one or more minterms, and    -   determining the lowest number of serial switches as the number        of literals in a cube having the largest number of literals and        covering a minterm not covered by a cube having a lower number        of literals.

In the ninth or tenth aspects, the determining step may comprise thesteps of:

-   -   determining, for each minterm, the cube covering the minterm and        having the smallest number of literals, and    -   determining the lowest number of serial switches as the number        of literals in a cube having the largest number of literals        among the determined cubes.

In addition, in the ninth or tenth aspects, the determining step maycomprise the steps of:

-   -   repeatingly identifying, in the covering table, a cube having a        largest number of literals and determining whether each minterm        which is covered by the identified cube is also covered by        another cube having a lower number of literals, if so, removing        the cube from the covering table,    -   until no cube can be removed, and    -   determining the lowest number of serial switches as the number        of literals in a cube having the largest number of literals in        the covering table.

As described above, an alternative is one in which the cubes are notremoved but marked and where the determining step is performed only onnon-marked cubes.

An eleventh aspect of the invention relates to a method of mapping aBoolean function (which may be described as a set of interconnectedlogic primitives, such as and-gates, or-gates, inverters or the like) ora network of switches, the method comprising:

-   -   for each of a plurality of parts of the function or the network,        determining a logic sub-function implemented thereby,        determining a lowest number of serial switches of the pull-up        network of the sub-function using the method according to the        ninth aspect, and determining a lowest number of serial switches        of the pull-down network of the sub-function using the method        according to the tenth aspect, and    -   selecting a subset of the determined parts, the parts of the        subset implementing the function, and where each part, for each        of the pull-up and pull-down networks of the sub-function        implemented by the part, has a lowest number of serial switches        lower than a predetermined value.

Preferably, the subset is selected such that a given cost function forthe overall function or network is minimized. This cost function may bethe total number of switches as described above.

A twelfth aspect of the invention relates to a method of improving anetwork or function, the method comprising:

-   -   defining a part of the function or the network, determining a        logic sub-function implemented thereby, determining a lowest        number of serial switches of the pull-up network of the        sub-function using the method according to the ninth aspect, and        determining a lowest number of serial switches of the pull-down        network of the sub-function using the method according to the        tenth aspect, and    -   replacing the part of the function or network by a network of        switches, in each network relating to a value of the function,        as derived in the eighth aspect.

A thirteenth aspect of the invention relates to a computer programadapted to control a processor to carry out the method according to anyof the sixth to twelfth aspects.

A fourteenth aspect of the invention relates to a circuit or gate fromthe group consisting of the networks illustrated in FIGS. 25-34.Naturally, this aspect, and the relating claim, also covers networksderivable from the networks in FIGS. 25-34, where the order of seriallyinterconnected switches has been altered, and/or in which two parallelbranches share a switch in the network of the claim whereas the sameparallel branches of a corresponding network each has a switch, or wheretwo parallel branches in a network of the claim each has a switchcontrolled by the same input and where the parallel branches of acorresponding network shares a switch controlled by that input.

In the following, preferred embodiments of the invention will bedescribed with reference to the drawing, wherein:

FIG. 1 illustrates a flow diagram for minimum length stacks,

FIG. 2 is a truth table for a function,

FIG. 3 illustrates a bridge-based 5-4 cell for the function of FIG. 2,

FIG. 4 illustrates a BDD-based 4-4 PTL for the function of FIG. 2,

FIG. 5 illustrates CSP CMOS cells obtained from the on-set functions ofthe function of FIG. 2,

FIG. 6 illustrates CSP CMOS cells obtained from the off-set functions ofthe function of FIG. 2,

FIG. 7 illustrates CSP CMOS cells (factorized) for the function (on-setequation) of FIG. 2,

FIG. 8 illustrates CSP CMOS cells (factorized) for the function (off-setequation) of FIG. 2,

FIG. 9 illustrates a covering table obtained from the on-set of thefunction of FIG. 2,

FIG. 10 illustrates a covering table obtained from the off-set of thefunction of FIG. 2,

FIG. 11 illustrates NCSP CMOS cells for the function of FIG. 2,

FIG. 12 illustrates an alternative NCSP CMOS cell to that of FIG. 11 a,

FIG. 13 illustrates a truth table for another function,

FIG. 14 illustrates a covering table obtained from the on-set of thefunction of FIG. 13,

FIG. 15 illustrates a covering table obtained from the off-set of thefunction of FIG. 13,

FIG. 16 illustrates NCSP CMOS cells for the on-set equations of thefunction of FIG. 13,

FIG. 17 illustrates NCSP CMOS cells for the off-set equations of thefunction of FIG. 13,

FIG. 18 illustrates NCSP CMOS cells for the function of FIG. 13,

FIG. 19 illustrates a circuit to be mapped with cells from a library,

FIG. 20 illustrates two different matchings for the same node on thecircuit of FIG. 19,

FIG. 21 illustrates two alternative coverings using the matchings ofFIG. 20,

FIG. 22 illustrates counting serial transistors by serial parallelassociation of the network of FIG. 19,

FIG. 23 illustrates the division of the circuit of FIG. 19 into twocells,

FIG. 24 illustrates the counting of serial transistors in the network ofFIG. 19 by the method of the invention,

FIGS. 25-34 illustrate examples of networks which are obtainable usingthe method of the invention.

A first preferred embodiment comprises a method of systematicallygenerating digital cells of complex gate functions with an optimal oroptimized length of stacked switches (switch chain) for the pull-up andpull-down networks of a Boolean function. This method is able togenerate optimized cell logic functions where the most used standardimplementations, such as the Complementary Serial/Parallel CMOS andPass-Transistor Logic, do not produce networks with minimum lengthtransistor chains. For these functions, new, efficient transistornetworks implementations have been obtained that will result in minimumlength switch stacks. The presented networks follow neither theComplementary Serial/Parallel CMOS nor the Pass-Transistor Logictopologies. In addition, it is possible to catalogue a selected set oflogic functions whose switch-based circuits are better implemented usingthe below method.

In the present description, each cell (circuit) is characterized by apair p-n, where p represents the length of its longest pull-up path andn represents the length of its longest pull-down path.

There are several ways to implement a switch network. The common factoramong these implementations are the presence of paths which pull up theoutput to logic one (pull-up network or pull-up plane) and paths whichpull down the output to logic zero (pull-down network or pull-downplane).

For the sake of compatibility with most of the circuits available today,the examples presented here will use transistors as switches (pMOS forpull-up plane and nMOS for pull-down plane). However, the methodpresented hereby is not restricted to transistors and may be used withany kind of switch available (valve, relay, nanotube, etc.).

In FIG. 2, an example of a function is given, and the preferred methodwill now be illustrated in relation to this function. An integer numberis used to represent the function, most of the time in hexadecimalradix. This number is built grouping the 4-bit output sets of thetruth-table. In the example presented in FIG. 2 the output compounds theinteger (0000 0001 1001 0111)₂=(0197)₁₆.

Naturally, a number of different networks may be generated whichembodies or carries out this function, a number of manners exist ofderiving these networks, and a number of manners exist of actuallyrepresenting these networks.

For example, in FIG. 3, a 5-4 bridge-based circuit is illustrated whichembodies the function of FIG. 2.

FIG. 4, a 4-4 PTL (Pass-Transistor Logic) network corresponding to thelogic function (0197)₁₆ shown in FIG. 2 is illustrated. There areseveral ways to implement a PTL network but the one presented in FIG. 4is based on a Binary Decision Diagram (BDD).

Another way of implementing a logic function is obtained by extracting arepresentative logic equation and mapping it into a serial/parallelswitch network. The prime irredundant equations for the function(0197)₁₆ can be obtained by two-level minimization. The logic equationeq.1 represents the on-set of the function (0197)₁₆ while the logicequation eq.2 represents the off-set for the same function.

FIGS. 5 and 6 show Complementary Serial/Parallel CMOS (CSP) networks forthe function (0197)₁₆. FIG. 5 presents the networks based on the on-setequation and FIG. 6 presents the networks based on the off-set. For eachCSP circuit in FIGS. 5 and 6, one plane is derived from the equation andthe other one as a topological complement.

In order to reduce the number of switches in the networks, both on-setand off-set equations (eq.1 and eq.2 respectively) can be factorized.Possible factorizations for the equations eq.1 and eq.2 are demonstratedas follows by eq.3 and eq.4.

This factorization leads to the optimized networks presented in FIGS. 7and 8.

Thus, it is seen that different networks with different numbers ofserial transistors/switches and different numbers of totaltransistors/switches are obtained by these different methods.

Thus, by simply selecting the optimal pull-up network and the optimalpull-down network independently of the method used for generating thenetwork, an optimized network may be obtained.

This may be implemented by simply deriving a large number of pull-upnetworks and a large number of pull-down networks and then finallydetermining which pull-up network and which pull-down network to use.

An alternative to that method is seen in FIG. 1, which is a diagramillustrating a manner of determining parameters of the optimal pull-upand pull-down networks. In this manner, the generation of pull-upnetworks and pull-down networks may be stopped once networks having theoptimal parameters have been derived.

In the methodology illustrated in FIG. 1, pull-up and pull-down networksare generated by different methods and then a pull-up/down pair whichrespects the lower bounds for the number of serial switches is selected.The lower bound is preferably evaluated for both on- and off-setextracted from the function under evaluation. Hence, the evaluation oflower bounds favours the construction of the covering tables for bothon- and off-set. FIG. 9 shows the covering table for the on-set of thefunction presented (0197)₁₆ while FIG. 10 shows the covering table forthe off-set of the same function.

From the covering table in FIG. 9 it is seen that the cube with moreliterals (ā·b·c·d) cannot be removed from the final cover as it is anessential prime implicant cube, meaning it is the only cube to cover oneof the implicant minterms. Hence, the lower bound for the number ofserial switches for the on-set is 4 (the number of literals in thecube). For the covering table in FIG. 10, the lower bound evaluated is3. Hence, the circuit with pull-up/down networks respecting the lowerbounds will be 3-4 or 4-3.

FIG. 11 shows implementations of minimum length transistor chains forthe example function (0197)₁₆. It is seen that none of theimplementations of FIGS. 2-8 have minimum length switch stacks. Evenworse is the fact that some circuit implementations, like the ones inFIGS. 5, 6, 7 and 8, may not even be feasible due to the long transistorstacks: a circuit is usually unfeasible for practical applications whenit has paths with more than 4 serial transistors. The theory behind theevaluation of the lower bound in path length for pull-up and pull-downnetworks in a circuit is further described in “Exact lower bound for thenumber of switches in series to implement a combinational logic cell.”,F. R. Schneider, R. P. Ribas, S. S. Sapatnekar, A. I. Reis.International Conference on Computer Design, October 2005, pp. 357-362.

Generally, the order of the switches in serial switch stacks is anotheroptimization that could be considered in order to generate circuits withbetter performance: switches with slower input slopes advantageouslycould be positioned closer to the output in order to improve the overallperformance, while nodes with more connected switches advantageouslycould be positioned far from the output in order to reduce fanoutcapacitance.

For instead, considering that the inputs d and d in the circuitspresented in FIG. 11 are the slowest ones, the transistors, having d andd as input signals, could be moved to a position closer to the output,so the negative impact in circuit's overall performance would bereduced. FIG. 12 shows the alternative network for the suggestedordering of FIG. 11 b, still maintaining the nodes of greater order(more connected switches) as far as possible from the output.

In order to better exemplify the lower bound evaluation used to choosethe correct networks for minimum transistor stacks, this will beillustrated with another function, the truth table of which isillustrated in FIG. 13. This function is a 5-input function whoserepresentative hexadecimal integer is (F1D12F33)₁₆.

The prime irredundant equations for the function (F1D12F33)₁₆ obtainedby two-level minimization are given in eq.5 for the on-set and eq.6 forthe off-set.

These equations were generated aiming at a smaller set of cubes.However, if one evaluates the lower bound just by looking for the cubewith more literals, it will be wrongly assumed that the lower bounds forthe function (F1D12F33)₁₆ should be 4-4. However, the covering table forthe on-set of this function (FIG. 14) shows that the cube (primeimplicant) with more literals on the equation eq.5 (striked-out line)can be removed without losing the cover of all minterms. In equationeq.7, an equivalent representation for equation eq.5 is given where thecube with four literals has been replaced by a pair of cubes with onlythree literals.

The off-set covering table in FIG. 15 shows that the same reductioncannot be done to the off-set equation eq.6 once in that the cubes withthe largest number of literals are essential prime implicants, whichmeans they cannot be removed from the final solution. It means that theevaluation of lower bounds for the function (F1D12F33)₁₆ should deliver3-4/4-3 circuits. The equations of eq.7 (on-set) and eq.6 (off-set) canbe further factorized, and possible results are provided by equationseq.8 and eq.9, respectively.

In FIG. 16 and FIG. 17, circuits using the regular CSP CMOS approach areshown using the factorized equations in eq.8 and eq.9, respectively. Thepull-up/down networks of these circuits were used in FIG. 18 to generateNCSP circuits with minimum length transistor chains.

The present embodiments may also be used to catalogue the functionswhere the previously used logic topologies will not produce minimumlength transistor chain implementations. For these functions a minimumlength switch chain implementation is obtainable, based on a key(hexadecimal integer) for finding the function. This catalogue presentsall the 4-input functions where a topologically serial/parallelcomplementary CMOS topology does not produce a minimum length transistornetwork. It also presents a catalogue with a set of feasible 5- and6-input negative unate functions (i.e. transistor chains with at most 4transistors) where CSP circuit do not respect lower bounds. However, themethod of generating minimum length transistor chains described herebycan be applied to any n-input function. FIGS. 25-34 illustrate suchnetworks which are obtained in this manner.

Another embodiment relates to technology mapping is well known as thesynthesis step where the choice of cells from a library that will beeffectively used in the final circuit layout are chosen. For instance,consider FIG. 19 that shows an equation to be mapped.

The first step in technology mapping is known as matching and itbasically identifies portions of the initial equation that may beimplemented by using cells from the library. For instance, FIG. 20 showstwo matchings at the output node of the equation in FIG. 19.

The second step in technology mapping is known as covering, and itchooses a set of matchings that completely implements the equation to bemapped. FIG. 21 shows two alternative complete coverings, each using oneof the alternative matchings presented in FIG. 20.

Technology mapping algorithms based on automatic library generatorsnormally performing a matching phase that is based on counting thenumber of serial transistors that a cell would have. Normally thiscounting is done by serial parallel association counting, as it is wellknown in previous art. FIG. 22 shows the serial parallel counting forthe equation in FIG. 19. It is possible to see that this equation willhave 5 serial transistors in one plane and 4 serial transistors in theother. These numbers are not minimal, as will be described furtherbelow, but they are the values effectively obtained by serial parallelassociation calculation, which is the known way of doing it. As forcurrent standard fabrication technologies, it is widely accepted that amaximum of 4 NMOS and 3 PMOS transistors in series is the limit ofacceptable for a single cell, the equation in FIG. 22 would not beimplemented as a single cell, as no valid matchings will be produced atthe output, due to the excessive number of serial transistors. As seenin FIG. 23, this function will, using the prior art method, beimplemented using two cells.

However, if the calculation is done using the above-mentioned methodaccording to the method, smaller values will result. Thus, it isactually possible, using the method of the invention, to providenetworks with even lower numbers of serial transistors, as shown in FIG.24. Thus, the present method allows the advantage of arriving at a trueminimum number of serial transistors, which results in larger portionsof the circuit to be feasible as single cells. This effect potentiallyproduces speed improvements as well as area and power savings due to theuse of a smaller number of cells. For instance, the circuit of theequation illustrated in FIG. 24 can be implemented as a single cell with3 and 4 serial transistors using the method according to the invention.

1. A method of deriving a switch network adapted to carry out apredetermined multiple-valued function and comprising a network for eachof the multiple values of the function, the method comprising: for atleast one of the networks relating to a value of the function: derivinga covering table for the pertaining value of the function and having anumber of cubes each covering one or more minterms, estimating thelowest number of serial switches in the network as the number ofliterals in a cube having the largest number of literals and covering aminterm not covered by a cube having a lower number of literals, andderiving the network on the basis of cubes of the covering table havinga number of literals smaller than or equal to the estimated lowestnumber of serial switches of the network relating to the value of thefunction, the network having a number of parallel paths, each parallelpath being defined by one cube and having a number of seriallyinterconnected switches each having an input corresponding to a literalof the cube.
 2. A method according to claim 1, wherein the deriving stepcomprises deriving the network from a subset of the cubes of thecovering table, where each cube in the subset covers at least oneminterm not covered by other cubes of the subset.
 3. A method accordingto claim 1, wherein the deriving step comprises the steps of:identifying two parallel paths each comprising a switch having the sameinput and changing one of the identified paths to share the switch ofthe other identified path with that input.
 4. A method according toclaim 1, wherein the deriving step comprises the steps of: determiningan ordering of the inputs of the switches, from lowest to highest,defining a direction in a path of the network, and interchangingpositions of two switches of the path if a lower order switch ispositioned, along the direction, before a higher order switch.
 5. Amethod of deriving a switch network adapted to carry out a predeterminedBoolean function and comprising a pull-up network and a pull-downnetwork, the method comprising: deriving from the function a firstcovering table having a number of cubes each covering one or moreminterms, estimating the lowest number of serial switches in the pull-upnetwork as the number of literals in a cube of the first covering tablehaving the largest number of literals and covering a minterm not coveredby a cube having a lower number of literals, deriving the pull-upnetwork on the basis of cubes of the first covering table having anumber of literals smaller than or equal to the estimated lowest numberof serial switches of the pull-up network, the network having a numberof parallel paths, each parallel path being defined by one cube andhaving a number of serially interconnected switches each having an inputcorresponding to a literal of the cube, deriving from the invertedfunction a second covering table having a number of cubes each coveringone or more minterms, estimating the lowest number of serial switches inthe pull-down network as the number of literals in a cube of the secondcovering table having the largest number of literals and covering aminterm not covered by a cube having a lower number of literals, andderiving the pull-down network on the basis of cubes of the secondcovering table having a number of literals smaller than or equal to theestimated lowest number of serial switches of the pull-down network, thenetwork having a number of parallel paths, each parallel path beingdefined by one cube and having a number of serially interconnectedswitches each having an input corresponding to a literal of the cube. 6.A method according to claim 5, wherein the deriving step comprisesderiving the network from a subset of the cubes of the covering table,where each cube in the subset covers at least one minterm not covered byother cubes of the subset.
 7. A method according to claim 5, wherein thederiving step comprises the steps of: identifying two parallel pathseach comprising a switch having the same input and changing one of theidentified paths to share the switch of the other identified path withthat input.
 8. A method according to claim 5, wherein the deriving stepcomprises the steps of: determining an ordering of the inputs of theswitches, from lowest to highest, defining a direction in a path of thenetwork, and interchanging positions of two switches of the path if alower order switch is positioned, along the direction, before a higherorder switch.
 9. A computer program adapted to control a processor tocarry out the method according to claim 5.